Software Cooling Function Enabler for 32bit Athlon Series on Win32
Coolon Project
Translated from Japanese automatically using eXcite Japan (Powered by BizLingo)

The software cooling function

With the software cooling function

Even when doing nothing by a computer, CPU always keeps functioning. Therefore even when usually doing nothing, CPU has fixed fever. When CPU isn't working by input waiting for a software cooler, it's basic action to restrain fever of CPU by the thing which issues a HALT order and makes CPU suspended temporarily.

When CPU isn't working in case of Windows, I enter idle process. Windows2000 and ACPI In Windows98 of a mode, an idle process, it itself issues a HALT order. KCPUCooler and WinCooler Windows The measure and HALT which are in the idle state by Hooke's doing idle process by a software cooler besides the standard An order is issued.

Further when there is software by which Hooke does idle process because the processor usage rate by which it's for a system monitor is calculated in time in the idle process, CPU is always judged to be working. Windows When using a software cooler besides the standard, it's for this that the processor usage rate always becomes 100 %.

Special circumstances of Athlon/Duron

The outline of the software cooling function is the above-mentioned street, but even if Athlon/Duron is different from other CPU and executes a HALT order, a phase rock loop continues, and CPU won't be in the low power consumption state (AMD is insisting on this reason with the purpose to which I return quickly from HALT.) It's done because of this that a general software cooler doesn't function in Athlon/Duron including the Windows standard.

It's necessary to separate north bridge from central processor unit bus at the time of HALT to do CPU in the low power consumption state at the time of HALT order execution in Athlon/Duron.

The software cooling function of Athlon/Duron, it becomes more effective.

There is setting in a configuration register of north bridge (CPU to Host Bridge) for whether north bridge is separated from central processor unit bus at the time of HALT. Then the software which makes the software cooling function effective in Athlon/Duron (CPUCooL,Hardware Sensors Monitor) changes this setting including this software.

It's seen as a simple account, but when the split up is made effective by composition of parts, other configurations and cashier's setting, movement becomes unstable, hangs and isn't so simple. Like being lucky changing the setting, and when working, please think.

Further BIOS just initializes this register for a start the time, and OS doesn't rewrite during operation. Therefore BIOS It's just established once after the initialization, and it's OK. Therefore CoolON isn't stationed.

Setting of each north bridge

Then bit18 of offset 60-63h of a configuration register of host bridge (Bus#0/Dev#0/Function#0) is setting as Halt Disconnect Enable, and when here is made 1, north bridge of AMD (751/761) can cut off. By the way, bit17 makes both of them 1 in CoolON in Stop Grant Disconnect Enable.

When bit7 of a register for 52 h makes here 1 in case of KT133 system in Disconnect Enable When STPGNT Detected by north bridge of VIA, it can be cut off. KT266 More Disconnect Enable When Halt Detected uses 92h instead of 52h by the system, and is added to bit1 of 95h, and it's necessary to make both of them 1. KT400 The 92h/95h is changed to D2h/D5h by the system. KT880 has moved to a register for for 82 h/85 h of HOSUTOBURRIJJI Function#1.

By north bridge of SiS, 730 The system 6Bh and 735-745 6Ah and bit0 by which after 746 is 6Ch are C1 (Halt) Disconnect. bit3 of 6Ah has information as S1 (StopGrant) Disconnect in SiS735, but it usually seems to be here effectively.

It's in-depth obscurity about north bridge of nVidia, but when bit4 of 6Fh is set to 11b in 1 in nForce2, split up seems able to do bit3-2 of E7h in nFroce. Further nForce2 400 When bit 7-5 of 6Fh isn't set to 000b by the system, the M which produces less effect/B (BIOS) exists.