There are no DIP switch and BIOS setting to which FSB266/333 is changed by recent SocketA M/B, and for the M/B side to judge FSB automatically, there is the M it isn't possible to use CPU of FSB266 for which in FSB333 compulsorily/B.
You can think GIGABYTE GA-7VAXP Ultra I'm using at present will use it in FSB333 by this type of M/B and use bought Thoroughbred 1800 only by original FSB266 (tear). "Well, I'm here and don't do an unnecessary thing!" for, it feels like (do).
CPU of FSB333 was added from Thoroughbred of CPUID 0681. All together, a pin as FSB_Sense [1:0] is also added by CPU to this. This is the pin to decide FSB of CPU literally and is the following meaning.
AG31 pin and FSB_Sense  are allotted to AH30 pin ( These pins are NC by CPU to Palomino.), and when it's 0 (zero), FSB_Sense  is pulled down on the CPU side, and it's opening (NC) at 1. I have done pull finish of these pins on the M/B side by M which corresponds to FSB_Sense pin/B, so M/B judges FSB_Sense pin as FSB266 by undealt CPU, and judges FSB automatically based on pin setting by CPU corresponding to FSB_Sense pin.
|1||1||133MHz x 2|
|0||1||166MHz x 2|
FSB_Sense CPU Using a bridge of where FSB_Sense  is at least for the thing pulled down on the side, it's connected with pull-down resistor and I can think it'll be 1 (FSB266) when 0 (FSB333) is cut when the bridge is closed. When there is a bridge where I'm compared CPU of FSB333 and FSB266, closed by FSB333 and cut with FSB266 when saying conversely, that It's said to be FSB_Sense , it'll be. After the picture which appears on various sites was compared, the 2nd reached a conclusion as FSB_Sense  from the right in L12 bridge.
The bridge construction of Thoroughbred is also cut with CPUID 0680 certainly the 2nd from the right in L12 bridge of 0680 where even 0681 is same and exists in only FSB266 at all. Therefore even if it's from 0681 that FSB333 was added, I can think pull-down resistor of FSB_Sense  is mounted on 0680.
Because that was it, Thoroughbred I have was 0860, but when closing the 2nd from the right in L12 bridge, it was said that FSB266/333 would also move as FSB333 by automatic judgment M/B, and I experimented.
A traditional pencil (actually, core of a mechanical pencil of 0.5mm 4B) was used for bridge closure. But, laver of a core is bad by an organic package (The terminal surface may be insulated by a coating to the top.), so, even if it fills in color of a bridge just as it is, it can't close. Then, how is it, when I say whether it's done, it'll be a sandpaper and I rub around the bridge which fills in color lightly, and, the package surface, it's rough, it's key to do it (As well as, when I have that, I'll peel off a coating in the terminal surface.) If it filled in color of a bridge with a sandpaper of #360 which was in hand after it was rubbed, I came to move in FSB333. It's being used in this state from 2003/01/25, former, if, a problem doesn't generate time in particular.
Thoroughbred 1800 of FSB266 is 133MHz x 11.5 = 1533MHz, this, in simplicity FSB333 When I change, it's 166MHz x 11.5 = 1916MHz. When it'll be over clock to here, I don't know whether it moves. Because the magnification of L1 closure is variable, Thoroughbred has to lower the magnification beforehand by a DIP switch and BIOS setting.
It's no problem in particular by usual movement, but when FSB333 changes, the minor problem that the CPU name which can be acquired by an expansion CPUID order is "AMD Athlon (tm)", not "AMD AthlonXP (tm) 1800 " generates low clock Thoroughbred. CPU of POST It's expanded in great indication This indication is also "AMD Athlon (tm)" of course by BIOS with CPUID, so it may be feeling vice a little. Expanding They seem to be generating a CPU name from a name table in the CPU by FSB and assortment of the magnification in CPUID, and when it's combination in assumption outside, it seems to be "AMD Athlon (tm)".